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74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs
August 1999 Revised October 1999
74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT18825 contains eighteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 18-bit operation.
Features
s Broadside pinout allows for easy board layout s Separate control logic for each byte s Extra data width for wider address/data paths or buses carrying parity s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:
Order Number 74ACT18825SSC 74ACT18825MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn I0-I17 O0-O17 Description Output Enable Input (Active LOW) Inputs Outputs
FACTTM, FACT Quiet SeriesTM and GTOTM are trademarks of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS0500292
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74ACT18825
Functional Description
The ACT18825 contains eighteen non-inverting buffers with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independently of the other. The control pins may be shorted together to obtain full 8-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Truth Table
Inputs Byte 1 (0:8) Byte 2 (8:17) OE1 L H X L L H L OE2 L X H L L H L OE3 L L L H X H L OE4 L L L X H H L I0-I8 I9-I17 O0-O8 O9-O17 H X X L H X L H L H X X X L H Z Z L H Z L H L H Z Z Z L Outputs
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance
Logic Diagram
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74ACT18825
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Storage Temperature 50 mA -65C to +150C -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (Vt) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current Minimum Dynamic Output Current (Note 3) 5.5 5.5 5.5 5.5 5.5 0.6 8.0 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.5 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 5.0 1.0 1.5 80.0 75 -75 A A mA A mA mA V Units V V V Conditions VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC -2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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74ACT18825
AC Electrical Characteristics
VCC Symbol tPHL tPLH tPZL tPZH tPLZ tPHZ Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time (V) (Note 4) 5.0 5.0 5.0 Min 2.0 2.0 2.0 2.0 1.5 1.5 TA = +25C CL = 50 pF Typ 5.3 5.6 6.3 6.5 4.5 5.1 Max 8.4 8.7 9.6 9.7 7.3 8.5 TA = -40C to +85C CL = 50 pF Min 2.0 2.0 2.0 2.0 1.5 1.5 Max 9.0 9.2 10.3 10.4 7.6 8.8 ns ns ns Units
Note 4: Voltage Range 5.0 is 5.0V 0.5V.
Capacitance
Symbol CIN CPD Parameter Input Pin Capacitance Power Dissipation Capacitance Typ 4.5 95 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
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74ACT18825
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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